1. Field of the Invention
The present invention relates to a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus.
2. Description of the Related Art
In a solid-state imaging device configured with unit pixels each including a photoelectric converter, a charge-voltage converter, and a transfer gate part to transfer a charge accumulated by the photoelectric converter to the charge-voltage converter, generally denoising processing by correlated double sampling is executed in order to remove noise in reset operation. Hereinafter, the charge-voltage converter will be represented as the FD (floating diffusion) part. The systems of the denoising processing include a system in which the denoising is performed by digital signal processing and a system in which the denoising is performed by analog signal processing.
As a solid-state imaging device that executes the denoising processing by e.g. digital signal processing, a solid-state imaging device equipped with column-parallel analog-digital converters (ADCs; AD conversion circuit) is known (refer to e.g. Japanese Patent Laid-open No. 2006-340044 (hereinafter, Patent Document 1)). In this solid-state imaging device, the ADCs are disposed on a column-by-column basis for the matrix arrangement of the unit pixels.
In the solid-state imaging device equipped with column-parallel ADCs, a reset level Vrst read out first is set as a reference voltage Vzr of the AD conversion circuit, and the reset level Vrst and a signal level Vsig are AD-converted by using this reference voltage Vzr. Specifically, by equalizing the reference voltage Vzr to the reset level Vrst, the swing |Vsig-Vrst| of the pixel output based on the signal charge can be allowed to stably fall within the input voltage range of the AD conversion circuit even if the reset level Vrst varies due to noise.
In general, the reference voltage Vzr of the AD conversion circuit can be adjusted only within a range sufficiently narrower than the input voltage range of the AD conversion circuit. Therefore, as the reference voltage Vzr of the AD conversion circuit, a signal whose variation width is stably limited, like the reset level Vrst is preferable. In contrast, a signal whose voltage greatly swings depending on the amount of incident light, like the signal level Vsig, is not suitable as the reference voltage Vzr of the AD conversion circuit.
The denoising processing in the related-art solid-state imaging device like the above-described solid-state imaging device equipped with column-parallel ADCs is based on the premise that the reset level Vrst is first read out and the signal level Vsig is read out immediately after this reset level Vrst. In contrast, in a solid-state imaging device in which the reset level Vrst cannot be read out immediately before the signal level Vsig, before AD conversion of the signal level Vsig of a certain unit pixel, the reference voltage Vzr cannot be acquired from the same pixel.
Examples of the solid-state imaging device in which the reset level Vrst cannot be read out immediately before the signal level Vsig include a complementary metal oxide semiconductor, namely CMOS image sensor having the global exposure function (refer to e.g. Japanese Patent Laid-open No. 2001-238132). In this CMOS image sensor, in order to realize collective exposure of all pixels, a charge generated in the photoelectric converter is transferred to the FD part simultaneously in all pixels and readout operation is sequentially carried out from the state in which the signal charge is retained in this FD part.
In addition, the examples of the solid-state imaging device in which the reset level Vrst cannot be read out immediately before the signal level Vsig include a CMOS image sensor having a memory part to retain a photocharge transferred from the photoelectric converter separately from the charge-voltage converter (refer to e.g. Japanese Patent Laid-open No. 2009-020172). Moreover, the examples include a CMOS image sensor in which a photocharge generated at a PN junction is directly read out by an amplification transistor (refer to e.g. “128×128 CMOS PHOTODIODE-TYPE ACTIVE PIXEL, SENSOR WITH ON-CHIP TIMING, CONTROL AND SIGNAL CHAINELECTRONICS” SPIE, vol. 2415, Charge-Coupled Devices and Solid State Optical Sensors V, paper no. 34 (1995)), and an image sensor using an organic photoelectric conversion film (refer to e.g. Japanese Patent Laid-open No. 2008-228265).
In the solid-state imaging device, the FD part is reset once e.g. in collective transfer in all pixels or at the start of exposure, so that a signal charge has been already accumulated or retained in the FD part at the timing of signal readout. Therefore, the following operation is necessary to remove fixed pattern noise due to e.g. threshold variation of the amplification transistor. Specifically, as shown in FIG. 24, after the signal level Vsig is read out, the FD part is set to a predetermined potential and this predetermined potential is read out as the reset level Vrst.
However, in the solid-state imaging device in which signal readout is performed with a signal charge retained in the FD part for collective exposure of all pixels and the solid-state imaging device in which a signal charge is directly accumulated in the FD part and signal readout is performed, the FD part cannot be set to the predetermined potential immediately before readout of the signal level Vsig. In this case, the reference voltage for AD conversion of the signal level cannot be acquired. Thus, a predetermined voltage is generated by e.g. external application or a resistor array and this predetermined voltage is supplied to the AD conversion circuit as the reference voltage (refer to e.g. Japanese Patent Laid-open No. 2006-020172).